The present invention relates to a semiconductor device and a method of producing the semiconductor device. In particular, the present invention relates to a semiconductor device having a body contact for pulling out hot carrier generated in a channel area, and a method of producing the semiconductor device.
A conventional semiconductor substrate having a silicon layer on a wafer with insulation property includes a silicon on insulator (SOI) substrate, a silicon on sapphire (SOS) substrate, and the likes.
In the SOI substrate, a buried oxide layer (refer to as a BOX layer) is formed in a single crystal silicon substrate. That is, the SOI substrate has a three-layered structure formed of the silicon substrate, the BOX layer formed on an upper surface of the silicon substrate, and a silicon layer formed on an upper surface of the BOX layer. In the SOS substrate, a silicon layer is formed on a sapphire wafer through epitaxial growth.
In the SOI substrate, the BOX layer is formed in the silicon layer as an insulation layer to electrically separate individual element areas formed in an element forming area. In the SOS substrate, an element separation area is formed in the silicon layer with a depth reaching to the sapphire wafer to electrically separate individual element areas formed in an element forming area.
In these cases, each of the element areas has a side surface and a backside surface covered with the element separation area and the silicon layer. Accordingly, in the SOI substrate and the SOS substrate, it is possible to separate the element areas more securely as compared with a semiconductor substrate without an insulation layer. As a result, when a transistor is formed in the element area of the SOI substrate or the SOS substrate, it is possible to reduce an influence of other transistors. That is, with the SOI substrate or the SOS substrate, it is possible to produce a transistor with high tolerance against crosstalk noises without causing latch up.
As described above, in the semiconductor substrate such as the SOI substrate and the SOS substrate, individual transistors formed thereon are completely insulated with each other. Accordingly, when hot carrier is generated in a channel area (body area), hot carrier tends to accumulate in an area around a source area. When hot carrier accumulates in an area around the source area, it is known that a parasitic bipolar effect would occur, thereby causing a fluctuation in transistor characteristics such as decrease in a threshold voltage, increase in a current between source and drain, and the likes.
In order to suppress the parasitic bipolar effect, a conventional semiconductor device is adopted to have a body-tie structure or a source-tie structure.
FIG. 6 is a schematic plan view showing a conventional semiconductor device having the body-tie structure. In the conventional semiconductor device having the body-tie structure, a conductive type impurity similar to that of a channel area 103 is introduced at a high concentration in an area called a high-concentration body area 105.
The high-concentration body area 105 is arranged adjacent to end portions of the channel area 103 and first and second main electrode areas 107a and 107b sandwiching the channel area 103. The high-concentration body area 105 is formed of an expansion portion extending from the channel area 103 in a channel width direction.
In the conventional semiconductor device having the body-tie structure, a contact or body contact 109 is formed on the high-concentration body area 105 away from the channel area 103 and the first and second main electrode areas 107a and 107b for applying a potential to the high-concentration body area 105. With this structure, hot carrier generated in the channel area 103 moves to the high-concentration body area 105, and is pulled out through the body contact 109.
FIG. 7 is a schematic plan view showing a conventional semiconductor device having the source-tie structure. In the conventional semiconductor device having the source-tie structure, a high-concentration body area 115 is formed in an element area 111. The high-concentration body area 115 is arranged in an area next to a source area, i.e., a first main electrode area 113a or a second main electrode area 113b functioning as the source area, opposite to a channel area 117. In the structure shown in FIG. 7, the first main electrode area 113a is provided as the source area.
In the conventional semiconductor device having the source-tie structure, a hot carrier moving area 119 is provided as an expansion area extending from the channel area 117 in a channel width direction. A conductive type impurity similar to that of the high-concentration body area 115 and the channel area 117 is introduced into the hot carrier moving area 119.
In the conventional semiconductor device having the source-tie structure, similar to the conventional semiconductor device having the body-tie structure, a body contact 121 is disposed away from the source area 113a for applying a potential to the high-concentration body area 115. With this structure, hot carrier generated in the channel area 117 moves to the high-concentration body area 115 through the hot carrier moving area 119, and is pulled out through the body contact 112.
As described above, in the conventional semiconductor device having the body-tie structure and the conventional semiconductor device having the source-tie structure, in addition to the channel area 103 or 117, and the first and second main electrode areas 107a and 107b or 113a and 113b as the source and drain areas constituting an ordinal transistor, it is necessary to provide the high-concentration body area 105 or 115 and the hot carrier moving area 119.
Further, in order to suppress an influence of the high-concentration body area 105 or 115 and the hot carrier moving area 119 on the transistor, it is necessary to electrically separate the high-concentration body area 105 or 115 and the hot carrier moving area 119 from the channel area 103 or 117 and the first and second main electrode areas 107a and 107b or 113a and 113b. That is, for the electrical separation, it is necessary to provide a separation gate electrode portion 127 or 129 in addition to a channel control gate electrode portion 123 or 125.
In particular, in the conventional semiconductor device having the body-tie structure, the separation gate electrode portion 127 is provided on the high-concentration body area 105 in a length over the first main electrode area 107a, the channel area 103, and the second main electrode area 107b. In the conventional semiconductor device having the source-tie structure, the separation gate electrode portion 127 is provided on the hot carrier moving area 119 in a length over the high-concentration body area 115, the first main electrode area 113a, the channel area 117, and the second main electrode area 113b. 
Accordingly, while an ordinal gate electrode portion has an I character shape, the separation gate electrode portion 127 or 129 has a T character shape. As a result, as opposed to an ordinal transistor, an area of one single element area increases, thereby making it difficult to reduce a size of the element and produce a highly integrated device.
Further, in the conventional semiconductor device having the body-tie structure and the conventional semiconductor device having the source-tie structure, it is necessary to provide the separation gate electrode portions 127 and 129, thereby increasing a gate area. Accordingly, a gate resistance tends to increase, and a shielding frequency tends to deteriorate.
Patent Reference has disclosed a semiconductor device having a minimized element area. In the semiconductor device disclosed in Patent Reference, first and second main electrode areas as a source area and a drain area are formed in a silicon layer, and have a depth not reaching a BOX layer. A high-concentration body area is formed in an area opposite to a channel area of the first or second main electrode area. A conductive type impurity similar to that of the channel area is introduced into the high-concentration body area at a high concentration.
In the semiconductor device disclosed in Patent Reference, the high-concentration body area is insulated from the first and second main electrode areas with an oxide layer (first separation area) formed with a well-known local oxidation of silicon (LOCOS) method. A second separation area is provided between chips or elements for insulating the chips or elements. Different from the second separation area, the first separation area has a depth not reaching the BOX layer. Further, a body contact is formed on the high-concentration body area for pulling out hot carrier.
As described above, in the semiconductor device disclosed in Patent Reference, the first and second main electrode areas and the first separation area are formed in the silicon layer and have depths not reaching the BOX layer. Accordingly, hot carrier may be able to move from the channel area to the high-concentration body area through an area (lower area) in the silicon layer between the first or second main electrode area and the first separation area, and the BOX layer.
Accordingly, when a potential is applied to the high-concentration body area through the body contact, hot carrier generated in the channel area moves to the high-concentration body area through the lower area of the first or second main electrode area and the first separation area in the silicon layer. After moving to the high-concentration body area, hot carrier is pulled out through the body contact.
Accordingly, in the semiconductor device disclosed in Patent Reference, it is not necessary to provide the hot carrier moving area as in the conventional semiconductor device. Further, it is not necessary to provide the separation gate electrode portion in addition to an ordinal gate electrode portion. Accordingly, it is possible to minimize the element area. Further, it is possible to prevent a gate resistance from increasing due to an enlarged gate area and a shielding frequency from deteriorating.    Patent Reference: Japanese Patent Application No. 2003-124345
As described above, in the semiconductor device disclosed in Patent Reference, the first and second main electrode areas as the source area and the drain area have depths not reaching the BOX layer. Accordingly, a contact area between the channel area and the drain area increases, so that a contact capacity increases when the transistor is driven. As a result, the semiconductor device disclosed in Patent Reference is not suitable for a high-speed operation.
Further, in the semiconductor device disclosed in Patent Reference, when the transistor is driven, a depletion layer tends to extend in the lower area of the drain in the silicon layer. Accordingly, when a gate length decreases accompanied with a decrease in a size of the element, a threshold voltage decreases, thereby causing a short channel effect.
When the semiconductor device disclosed in Patent Reference is produced, the first separation area is formed with the LOCOS method, so that the first separation area has a depth not reaching the BOX layer. In this step, it is necessary to form the first separation layer away from the BOX layer, so that hot carrier can move through the lower area of the first separation area. However, it is difficult to accurately adjust a thickness of the oxide layer as the first separation area with the LOCOS method. Accordingly, in the semiconductor device disclosed in Patent Reference, it is difficult to obtain a sufficient distance between the first separation area and the BOX layer in the silicon layer. In an opposite case, the first separation area may reach the BOX layer.
The problem described above becomes apparent when the first separation area is formed in the SOI substrate coated with a thin silicon layer. When a sufficient distance is not obtained between the first separation area and the BOX layer, or the first separation area reaches the BOX layer, hot carrier generated in the channel area cannot move through the lower area of the first separation area. Accordingly, hot carrier thus generated does not move to the high-concentration body area, so that hot carrier cannot be pulled out through the body contact.
In view of the problems described above, an object of the present invention is to provide a semiconductor device using the SOI substrate, the SOS substrate, or a semiconductor substrate having an insulation layer. In the semiconductor device of the present invention, it is possible to minimize the parasitic bipolar effect without increasing an element area. Further, it is possible to reduce the short channel effect. Another object of the present invention is to provide a method of producing the semiconductor device.
Further objects and advantages of the invention will be apparent from the following description of the invention.